On chip adaptive jitter reduction hardware method for LVDS systems
US10148261B1 · kind B1 · utility
3Cited by
13References
20Claims
0Family size
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Key dates
| Filing date | Dec 18, 2017 |
| Grant date | Dec 4, 2018 |
| Priority date | — |
| Expiry date | Dec 18, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/21
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A low voltage differential signaling (LVDS) driver circuit, system, apparatus, and methodology are provided for controlling switching components in a primary current stage and a pre-emphasis current stage with an adaptive pre-emphasis gain tuning hardware control circuit arranged to provide control signals for periodically tuning a pre-emphasis gain setting for the secondary pre-emphasis current stage by selecting an optimum pre-emphasis gain setting from a plurality of pre-emphasis gain setting which minimizes an inter-symbol interference (ISI) jitter measure for the LVDS driver circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.