Current steering digital to analog converter with decoder free quad switching
US10148277B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 19, 2017 |
| Grant date | Dec 4, 2018 |
| Priority date | — |
| Expiry date | May 19, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/742
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed herein is a digital to analog converter including a first dynamic latch receiving a data signal and an inverse of the data signal. The first dynamic latch is clocked by a clock signal and configured to generate first and second quad switching control signals as a function of the data signal and the inverse of the data signal. A second dynamic latch receives the data signal and the inverse of the data signal, is clocked by an inverse of the clock signal, and is configured to generate third and fourth quad switching control signals as a function of the data signal and the inverse of the data signal. A quad switching bit cell is configured to generate an analog representation of the data signal as a function of the first, second, third, and fourth quad switching signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.