Apparatus and method for cancelling pre-cursor inter-symbol-interference
US10148469B2 · kind B2 · utility
1Cited by
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20Claims
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Key dates
| Filing date | May 1, 2017 |
| Grant date | Dec 4, 2018 |
| Priority date | — |
| Expiry date | May 12, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2201/04
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An apparatus is provided which comprises: a data slicer to receive first data sampled by a data clock; an edge slicer to receive second data sampled by an edge clock; and a Least Mean Square (LMS) circuitry coupled to the data and edge slicers, wherein the LSM circuitry is to generate a code to adjust a phase of one of data clock and/or edge clock relative to one another.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.