Low power timing, configuring, and scheduling
US10152111B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 9, 2017 |
| Grant date | Dec 11, 2018 |
| Priority date | — |
| Expiry date | Oct 9, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/70
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A network device includes a network interface circuit, a microprocessor, a timing circuit, and a microsequencer. The timing circuit is configured to, based on a primary timing signal, generate a time signature and switch the network device from an inactive state to an active state when the time signature satisfies a predetermined threshold length of time for packet transmission. The microsequencer circuit is configured to, in response to the network device being switched to the active state, activate and configure the network interface circuit for the packet transmission, independent of the microprocessor and delays encountered by the microprocessor. The device also reduces energy consumption by using a lower frequency secondary oscillator to maintain timing information when a higher frequency primary oscillator is inactivated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.