Apparatus and method for operating a power amplifier array with enhanced efficiency at back-off power levels
US10153731B2 · kind B2 · utility
3Cited by
2References
16Claims
0Family size
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Key dates
| Filing date | Oct 23, 2017 |
| Grant date | Dec 11, 2018 |
| Priority date | — |
| Expiry date | Nov 5, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B2001/045
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus, comprising has an array of power amplifiers. A power detector collects a power signal applied to the array of power amplifiers. Digital logic is connected to the array of power amplifiers and the power detector. The digital logic is configured to evaluate the power signal and select an array pattern from a set of array patterns and generate a control signal to implement the array pattern on the array of power amplifiers. Each array pattern in the set of array patterns includes at least one operative power amplifier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.