Integrated circuitry and methods for reducing leakage current
US10153768B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2018 |
| Grant date | Dec 11, 2018 |
| Priority date | — |
| Expiry date | Feb 28, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/9605
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Input/output circuitry includes a first PMOS device and a first NMOS device having first current electrodes are connected to each other and a pad. First selection circuitry, when the I/O circuitry is disabled, provides a first supply voltage to a control electrode and an N-well of the first PMOS device when the pad voltage is between the first and second supply voltages and to directly provide the pad voltage to the control electrode and the N-well of the first PMOS device when the pad voltage is greater than the first supply voltage. Similarly, second selection circuitry, when the I/O circuitry is disabled, provides a second supply voltage or directly provides the pad voltage to a control electrode and a P-well of the first NMOS device depending on whether the pad voltage is between the first and second supply voltages or less than the second supply voltage, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.