Transconductor circuit for a fourth order PLL
US10153774B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 27, 2017 |
| Grant date | Dec 11, 2018 |
| Priority date | — |
| Expiry date | Jan 27, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase locked loop (PLL) circuit and a method for providing a transconductance in the PLL involve forming an input voltage to an operational amplifier by a loop filter. A voltage output of the operational amplifier controls a plurality of current mirrors. A current is formed through a first one of the current mirrors as a function of the input voltage, a resistance of a resistor, and a reference voltage. The reference voltage is directly provided by, or derived from, a reference signal. A second voltage formed in the first current mirror is fed back to the operational amplifier to maintain the current through the first current mirror, which current is then mirrored into at least a second one of the current mirrors to form an output current proportional to a difference between the input voltage and the reference voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.