Patent · US Active

Use of error correcting code to carry additional data bits

US10153784B2 · kind B2 · utility

0Cited by

5References

21Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Daniel Greenspan · Madison, US
Asaf Rubinstein · Nes Ziona, IL
Julius Mandelblat · Haifa, IL

Key dates

Filing date	Jan 23, 2017
Grant date	Dec 11, 2018
Priority date	—
Expiry date	Jan 30, 2037

Classification

Technology area (CPC H)Electricity
CPC primaryH03M13/19
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

Integrated circuits, systems and methods are disclosed in which data bits protected by error correction code (ECC) detection and correction may be increased such that a combination of primary and additional bits may also be ECC protected using existing ECC allocation, without affecting ECC capabilities. For example, the additional bits may be encoded into phantom bits that are in turn used in combination with the primary bits, to generate an ECC. This ECC may then be combined with the primary bits to form a code word. The code word may be transmitted (or stored) so that when the data bits are received (or retrieved), assumed values of the phantom bits may be decoded, using the ECC, back into the additional bits without the phantom bits or the additional bits ever having transmitted (or stored).

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.