Generating high-speed test traffic in a network switch
US10153962B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 20, 2016 |
| Grant date | Dec 11, 2018 |
| Priority date | — |
| Expiry date | Nov 29, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L43/106
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Communication apparatus includes multiple interfaces connected to a packet data network, and a memory coupled to the interfaces and configured as a buffer to contain packets received through ingress interfaces while awaiting transmission to the network via respective egress interfaces. Packet processing logic is configured, upon receipt of a test packet through an ingress interface of the apparatus, to allocate a space in the buffer for storage of a single copy of the test packet, to replicate and transmit sequentially multiple copies of the stored copy of the test packet through a designated egress interface, to receive an indication of a number of copies of the test packet that are to be transmitted, and responsively to the indication, to terminate replication of the test packet and release the allocated space in the buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.