Method of producing a fine line 3D non-planar conforming circuit
US10154584B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 28, 2016 |
| Grant date | Dec 11, 2018 |
| Priority date | — |
| Expiry date | Jul 28, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/09872
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method of producing a non-planar conforming circuit on a non-planar surface includes creating a first set of conforming layers. The first set of conforming layers is created by applying an oxide dielectric layer to the surface, applying a conductive material layer to the oxide dielectric layer, applying a resist layer to the conductive material layer, patterning the resist layer according to a desired circuit layout, etching the surface to remove exposed conductive material, and stripping the resist layer. The process may be repeated to form multiple layers of conforming circuits with electrical connections between layers formed by blind microvias. The resulting set of conforming layers can be sealed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.