Addressable ring oscillator test chip
US10156605B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 20, 2015 |
| Grant date | Dec 18, 2018 |
| Priority date | — |
| Expiry date | May 11, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An addressable ring oscillator test chip includes: a plurality of ring oscillator test units, and a peripheral structure including peripheral circuits and PADs. The peripheral circuits share a first power source and a first grounding. Each test unit is associated with an independent power source to thereby decrease voltage drop resulting from wiring and to reduce the influence from other test units. A method of generating a variety of ring oscillators includes: generating a cell template corresponding to a basic unit, including defining a parameterized cell template; generating a ring oscillator based on the cell template, including generating ring oscillators of different stages by selecting different parameters of the cell template; realizing internal connections of the ring oscillator; and generating an instantiated ring oscillator by replacing cell templates with corresponding basic units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.