On-chip sequence profiler

US10156610B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Benedikt Geukes · Stuttgart, DE
• Manfred Walz · Pfalzgrafenweiler, DE
• Matteo Michel · Chemnitz, DE

Key dates

• Filing date: May 3, 2017
• Grant date: Dec 18, 2018
• Expiry date: May 3, 2037

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/318583
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A method, circuit, and design structure for an on-chip sequence profiler involves a programmable matrix and FSM in a logic circuit, a first latch receiving a scan path bit sequence and a first clock signal and generating a first output to control a select input of a first multiplexer, a first multiplexer selecting among functional path bit sequences and outputting a bit sequence to a second latch, a second latch receiving the bit sequence from the first multiplexer and a second clock signal via a second multiplexer and outputting a bit sequence to a logic circuit, a logic circuit receiving the bit sequence from the second latch and outputting a clock control signal to the clock and a second selector control signal to the second multiplexer, and a second multiplexer receiving a second clock signal from the clock and outputting the second clock signal to the second latch.