Cache memory clock generation circuits for reducing power consumption and read errors in cache memory
US10156887B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 29, 2016 |
| Grant date | Dec 18, 2018 |
| Priority date | — |
| Expiry date | Nov 6, 2036 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Cache memory clock generation circuits for reducing power consumption and read errors in cache memory are provided. In one aspect, a cache memory clock generation circuit employs detector circuit configured to receive a way address and generate a one way hit signal indicating if cache read request results in a single way hit. Clock and enable circuit is configured to generate a cache clock signal in response to a system clock signal and a cache enable signal, and generate a cache read enable signal in response to the cache clock signal and a read enable signal. Gating circuit is configured to generate a read clock signal in response to one way hit signal, cache clock signal, and cache read enable signal. Sense amplifier clock generation circuit is configured to generate sense amplifier clock signal in response to the read clock signal having a defined pulse width.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.