Robust boot block design and architecture
US10157087B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 14, 2017 |
| Grant date | Dec 18, 2018 |
| Priority date | — |
| Expiry date | Jul 14, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/02335
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock generator circuit includes an internal reference clock generator, a sequential circuit, and a pulse generator circuit. The internal reference clock generator circuit receives a clock buffer signal, a reset signal, and provides a first clock signal. The sequential circuit receives the first clock signal, and provides an internal reference clock signal based on the first clock signal. The pulse generator circuit receives the internal reference clock signal, a slow ring oscillator clock signal, and the reset signal. The pulse generator circuit counts a number of internal reference clock signals cycles for each cycle of the slow ring oscillator clock signal, and generates a pulse signal in response to the number being equal to zero during a cycle of the slow ring oscillator clock signal. The pulse signal toggles the flip-flop clock circuit to recover from a deadlock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.