Computing architecture with co-processor
US10157156B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Dec 31, 2017 |
| Grant date | Dec 18, 2018 |
| Priority date | — |
| Expiry date | Jan 4, 2038 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A coprocessor (PL) is disclosed. The PL includes a memory router, at least one collection block that is configured to transfer data to/from the memory router, each collection block includes a collection router that is configured to i) transfer data to/from the memory router, ii) transfer data to/from at least one collection router of a neighboring collection block, and iii) transfer data to/from blocks within the collection block, and at least one programmable operator that is configured to i) transfer data to/from the collection router, and ii) perform a programmable operation on data received from the collection router.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.