Multi-die memory device
US10157660B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 10, 2017 |
| Grant date | Dec 18, 2018 |
| Priority date | — |
| Expiry date | Nov 10, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and includes first and second memory arrays. The first memory array couples to the first memory interface circuit. The second memory array couples to the second interface circuit. A second memory die is stacked with the logic die and the first memory die. The second memory die includes third and fourth memory arrays. The third memory array couples to the first memory interface circuit. The fourth memory array couples to the second memory interface circuit. Accesses to the first and third memory arrays are carried out independently from accesses to the second and fourth memory arrays.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.