Chip-scale cooling device having through-silicon vias and flow directing features
US10157817B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 26, 2018 |
| Grant date | Dec 18, 2018 |
| Priority date | — |
| Expiry date | Jan 26, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/427
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A cooling structure includes a first substrate layer including an array of cooling channels, a second substrate layer including a nozzle structure, an outlet manifold, and an outlet, a third substrate layer including an inlet, and inlet manifold, and one or more flow directing features are disposed within the inlet manifold. The one or more flow directing features include one or more micro-pillars extending into the cooling fluid flow path from the inlet manifold, the first substrate layer includes one or more first substrate layer through-holes, the second substrate layer includes one or more second substrate layer-through holes, and the third substrate layer includes one or more third-substrate layer through holes. The first substrate layer through-holes, the second substrate layer through-holes, and the third substrate layer through-holes are aligned into one or more TSVs and metallized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.