Semiconductor package including stepwise stacked chips
US10157883B2 · kind B2 · utility
4Cited by
9References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 11, 2017 |
| Grant date | Dec 18, 2018 |
| Priority date | — |
| Expiry date | Jan 11, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/00014
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package comprises a package substrate; a first chip stack and a second chip stack mounted side by side on the package substrate, wherein the first and second chip stacks each include a plurality of semiconductor chips stacked on the package substrate, wherein each of the semiconductor chips includes a plurality of bonding pads provided on a respective edge region thereof, wherein at least some of the plurality of bonding pads are functional pads, and wherein the functional pads occupy a region that is substantially less than an entirety of the respective edge region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.