Semiconductor element and fabrication method thereof
US10158046B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 28, 2017 |
| Grant date | Dec 18, 2018 |
| Priority date | — |
| Expiry date | May 28, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10H20/825
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor element has a metal protective layer and a metal oxide protective layer formed on the substrate to prevent the Si substrate surface from forming an amorphous layer; and a transition layer to reduce lattice difference between the metal oxide protective layer and the III-V-group buffer layer, thus improving crystal quality of the III-V-group buffer layer. A fabrication method can avoid formation of amorphous layers and cracks surrounding the Si substrate surface. A light-emitting diode (LED) element or a transistor element can be formed by depositing a high-quality multi-layer buffer structure via PVD and forming a GaN, InGaN or AlGaN epitaxial layer thereon.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.