Systems, circuits and methods for correcting dynamic error vector magnitude effects
US10158333B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 17, 2017 |
| Grant date | Dec 18, 2018 |
| Priority date | — |
| Expiry date | Apr 17, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/21145
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Systems, circuits and methods related to dynamic error vector magnitude (DEVM) corrections. In some embodiments, a power amplifier (PA) system can include a PA circuit having a plurality of amplification stages, and a bias system in communication with the PA circuit and configured to provide bias signals to the amplification stages. The PA system can further include a first correction circuit configured to generate a correction current that results in an adjusted bias signal for a selected amplification stage, with the adjusted bias signal being configured to compensate for an error vector magnitude (EVM) during a dynamic mode of operation. The PA system can further include a second correction circuit configured to change the correction current based on an operating condition associated with the PA circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.