Patent · US Active

Apparatus with electronic circuitry having reduced leakage current and associated methods

US10158354B2 · kind B2 · utility

4Cited by

3References

20Claims

0Family size

Assignee

Silicon Laboratories Inc. · US

Inventors

Arnab Kumar Dutta · Austin, US
Essam Atalla · Plano, US
Nicholas M. Atkinson · Austin, US

Key dates

Filing date	Feb 10, 2017
Grant date	Dec 18, 2018
Priority date	—
Expiry date	Feb 10, 2037

Classification

Technology area (CPC H)Electricity
CPC primaryH03K2217/0036
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

An apparatus includes an integrated circuit (IC), which includes complementary metal oxide semiconductor (CMOS) circuitry that includes a pull-up network coupled to a supply voltage and at least one input signal. The IC further includes a first metal oxide semiconductor (MOS) transistor coupled to the pull-up network and to a first bias voltage to reduce a gate-induced drain leakage (GIDL) current of the CMOS circuitry.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.