Digital phase locked loop and operating method of digital phase locked loop
US10158367B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 4, 2018 |
| Grant date | Dec 18, 2018 |
| Priority date | — |
| Expiry date | Jan 4, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/08
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital phase locked loop includes a digital phase detector, a digital loop filter, a digital controlled oscillator, a first divider that divides the second frequency of the oscillation signal depending on a first division value and outputs the division result as a division signal having a third frequency, a second divider that divides the second frequency of the oscillation signal depending on a second division value and outputs the division result as an output signal having a final frequency, a dithering block that receives the division signal and performs dithering on the first division value based on a preset pattern as cycles of the division signal pass, and a digital phase domain filter that performs second low pass filtering on the division signal in a phase domain and outputs the result of the second low pass filtering as the feedback signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.