Low-latency low-uncertainty timer synchronization mechanism across multiple devices
US10159053B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2016 |
| Grant date | Dec 18, 2018 |
| Priority date | — |
| Expiry date | Jan 5, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/70
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Systems, methods, and apparatus for synchronizing timing in devices coupled to a data communication link are disclosed. In one example, a first device programs a future system time value in a second device. The first device launches a low-latency trigger signal that causes the future system time value to be loaded into a timer of the second device when a timer of the first device matches the future system time value. The second device measures phase difference between the trigger signal and edges of a clock signal used for timing in the second device. The phase difference is measured using an oversampling clock that provides a desired measurement reliability. The measured phase difference permits the first device to accurately determine system time as applied to the second device. The trigger signal can be provided on existing pins used by first and second devices in accordance with communication protocols and specifications.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.