Control of data exchange between a primary core and a secondary core using a freeze process flag and a data frozen flag in real-time
US10162680B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2016 |
| Grant date | Dec 25, 2018 |
| Priority date | — |
| Expiry date | Apr 12, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/17325
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of exchanging data in a real-time operating system, between a primary core and a secondary core in a multi-core processor, includes executing a primary path via the primary core and executing a secondary path via the secondary core. The primary path is configured to be a relatively faster processing task and the secondary path is configured to be a relatively slower processing task. The method includes devising a freeze in process flag to have a respective flag status set and cleared by the primary path. The method includes devising a data frozen flag to have a respective flag status set and cleared by both the primary and the secondary paths. A component that is operatively connected to the multi-core processor may be controlled based at least partially on a difference between primary and secondary sets of calculations executed by the primary and secondary cores, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.