Patent · US Active

Method and system for implementing selective transformation for low power verification

US10162917B1 · kind B1 · utility

3Cited by

19References

21Claims

0Family size

Assignee

Cadence Design Systems, Inc. · US

Inventors

Fabiano Peixoto · Belo Horizonte, BR
Benjamin Chen · Los Altos, US
Chung-Wah Norris Ip · Cupertino, US
Björn Håkan Hjort · Handen, SE

Key dates

Filing date	Sep 30, 2016
Grant date	Dec 25, 2018
Priority date	—
Expiry date	Oct 6, 2036

Classification

Technology area (CPC G)Physics
CPC primaryG06F2119/06
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Disclosed is an improved approach to implement selective transformations of circuit components for performing verification. The approach looks at the observability of components to downstream properties to determine whether transformations are needed. The verification system leverages the knowledge about the behavior of the domains/components to identify only a subset of components that really need to undergo transformation.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.