Display driver circuitry with selectively enabled clock distribution
US10163385B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 16, 2015 |
| Grant date | Dec 25, 2018 |
| Priority date | — |
| Expiry date | Jan 17, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2330/021
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A display may have an array of pixels controlled by display driver circuitry. Gate driver circuitry supplies gate line signals to rows of the pixels. The gate driver circuitry may include gate driver integrated circuits. Each gate driver integrated circuit may have a shift register that supplies the gate line signals to the rows of pixels. The display driver circuitry supplies a clock signal to the gate driver integrated circuits. Each gate driver integrated circuit may have one or more clock trees that are selectively enable and disabled. Each gate driver integrated circuit may have a controller and a buffer that is controlled by a control signal from the controller. The buffer may be adjusted to supply or to not supply the clock signal to an associated clock tree in that gate driver integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.