SRAM margin recovery during burn-in
US10163493B2 · kind B2 · utility
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11Claims
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Key dates
| Filing date | May 8, 2017 |
| Grant date | Dec 25, 2018 |
| Priority date | — |
| Expiry date | May 8, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/417
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present invention provide systems and methods for re-balancing the stability of a SRAM cell. Embodiments of the present invention identify SRAM cells with negative voltage threshold margins and write a “zero” state bit with in the bi-stable flip-flop of the SRAM. Raising the voltage of the CMOS set containing the “zero” state bit and selective transistor biasing, skews the “zero” state bit towards the complementary “one” state bit. This induces an increase voltage thresholds of the identified SRAM cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.