RRAM array with current limiting element
US10163505B2 · kind B2 · utility
9Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 8, 2017 |
| Grant date | Dec 25, 2018 |
| Priority date | — |
| Expiry date | Dec 8, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/82
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A resistive random access memory (RRAM) circuit is provided. In some embodiments, the RRAM circuit has a plurality of RRAM cells. A bit-line decoder is configured to concurrently apply a forming signal to the plurality of RRAM cells. A current limiting element is configured to concurrently limit a current of the forming signal applied to the plurality of RRAM cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.