Method of forming source/drain contact
US10163720B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 23, 2017 |
| Grant date | Dec 25, 2018 |
| Priority date | — |
| Expiry date | Oct 23, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/8316
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods for fabricating semiconductor devices are disclosed. An exemplary method includes forming first spacers along sidewalls of a gate structure that is disposed over a substrate and between source/drain features. A first dielectric layer is formed over the substrate and recessed to expose upper portions of the first spacers. A spacer layer is then formed over the upper portions of the first spacers. A second dielectric layer is formed over the spacer layer, and a patterned masking layer is formed over the second dielectric layer. The second dielectric layer, the spacer layer, and the first dielectric layer are patterned. For example, exposed portions of the second dielectric layer, the spacer layer (forming second spacers disposed along the upper portions of the first spacers), and the first dielectric layer are etched to form a trench exposing the gate structure and the source/drain features. The trench is filled with a conductive material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.