Power semiconductor arrangement
US10163761B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 2015 |
| Grant date | Dec 25, 2018 |
| Priority date | — |
| Expiry date | Jun 17, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M7/003
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A power semiconductor device comprises a substrate; and power semiconductor components disposed on and connected thereto. The device includes a housing part with a housing wall having a first cutout. The device has, for making electrical contact therewith, a unitary load connection element which passes through the first cutout in an X direction, is electrically conductive, and has an outer connection section disposed outside the housing part and an inner connection section disposed within the housing part. A first bush which has an internal thread running in the X direction is rotationally fixed and movable in the X direction in the housing wall. The first outer connection section has a second cutout aligned with the first bush. The load connection element has a first holding element disposed near the first cutout, the holding element engaging in a groove in the housing wall which runs perpendicular to the X direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.