Stacked integrated circuit structure and method of forming
US10163856B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2015 |
| Grant date | Dec 25, 2018 |
| Priority date | — |
| Expiry date | Oct 30, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18162
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device, and a method of forming the device, are provided. The semiconductor device includes a first die having a first plurality of contact pads and a second die having a second plurality of contact pads. A substrate is bonded to a first contact pad of the first plurality of contact pads and a first contact pad of the second plurality of contact pads in a face-to-face orientation with the first die and the second die. A first through via extends through the substrate. Molding material is interposed between the first die, the second die and the substrate, the molding material extending along sidewalls of the first die, the second die, and the substrate. A second through via is positioned over a second contact pad of the first plurality of contact pads, the second through via extending through the molding material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.