Cell architecture with intrinsic decoupling capacitor
US10163884B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 2, 2017 |
| Grant date | Dec 25, 2018 |
| Priority date | — |
| Expiry date | Aug 4, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/992
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An IC includes an array of cells and a first set of endcap cells. The array of cells includes a first set of Mx layer power interconnects coupled to a first voltage, a first set of Mx layer interconnects, a second set of Mx layer power interconnects coupled to a second voltage source, and a second set of Mx layer interconnects. The first set of endcap cells includes first and second sets of Mx+1 layer interconnects. The first set of Mx+1 layer interconnects is coupled to the first set of Mx layer power interconnects and to the second set of Mx layer interconnects to provide a first set of decoupling capacitors. The second set of Mx+1 layer interconnects is coupled to the second set of Mx layer power interconnects and to the first set of Mx layer interconnects to provide a second set of decoupling capacitors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.