Memory device based on heterostructures of ferroelectric and two-dimensional materials
US10163932B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 25, 2016 |
| Grant date | Dec 25, 2018 |
| Priority date | — |
| Expiry date | Jul 25, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/701
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A ferroelectric random-access memory structure and processes for fabricating a ferroelectric random-access memory structure are described that includes using a molybdenum sulfide layer. In an implementation, a ferroelectric random-access memory structure in accordance with an exemplary embodiment includes at least one FeFET, which further includes a substrate; a back gate electrode formed on the substrate, the back gate electrode including a conductive layer; a gate dielectric substrate formed on the back gate electrode; a source electrode formed on the gate dielectric substrate; a drain electrode formed on the gate dielectric substrate; and a layered transition metal dichalcogenide disposed on the gate dielectric substrate and contacting the source electrode and the drain electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.