Method for forming an implanted area for a heterojunction transistor that is normally blocked
US10164081B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 18, 2014 |
| Grant date | Dec 25, 2018 |
| Priority date | — |
| Expiry date | Apr 18, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/854
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention relates to a method for manufacturing a heterojunction transistor (1), said method comprising the steps of: forming an implanted area (8) by ionically implanting magnesium, calcium, zinc, or fluorine in a first gallium nitride semiconductor layer (4), having a hexagonal crystalline structure, in the [0 0 0 1] orientation of said crystalline structure; forming a second semiconductor layer (6) on the first semiconductor layer so as to form an electron gas layer (5) at the interface between the first and second layers; and forming a control gate (75) over the second conductive layer (6) and vertically in line with the implanted area (8).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.