Method and device for auto-calibration of multi-gate circuits
US10164573B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Apr 8, 2016 |
| Grant date | Dec 25, 2018 |
| Priority date | — |
| Expiry date | Aug 24, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/62
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A differential-logic logic circuit chained with another differential-logic circuit comprises a first logic cell composed of back-gate transistors, the first cell having a first input for receiving a first input signal and having an output for delivering a first output signal, and a second logic cell complementary to the first cell, composed of back-gate transistors, the second cell having as many inputs as the first cell, each input able to receive an input signal complementary to the respective input signal of the first cell, the second cell having an output for delivering a second output signal complementary to the first output signal of the first cell. The first output signal of the first cell is applied to the back gate of each transistor of the second cell, and the second output signal of the second cell is applied to the back gate of each transistor of the first cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.