Patent · US Active

Phase-inverted clock generation circuit and register

US10164613B2 · kind B2 · utility

0Cited by

2References

10Claims

0Family size

Assignee

Huawei Technologies Co., Ltd. · CN

Inventors

Qi Chen · Maulburg, DE
Jianfu Zhong · Tangxia, CN
Qiuling Zeng · Shanghai, CN
Yu Xia · Northbrook, US

Key dates

Filing date	Aug 14, 2017
Grant date	Dec 25, 2018
Priority date	—
Expiry date	Aug 14, 2037

Classification

Technology area (CPC H)Electricity
CPC primaryH03K5/159
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A phase-inverted clock generation circuit is provided, where sources of a first PMOS and a second PMOS are connected to a power source, drains of the first PMOS and the second PMOS are connected to a source of a third PMOS, and a drain of the third PMOS is connected to a drain of a third NMOS; and the drain of the third PMOS is connected to a drain of a second NMOS, a source of the second NMOS is connected to a drain of a first NMOS, and a source of the first NMOS and a source of the third NMOS.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.