QC-LDPC coding methods and apparatus
US10164659B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 12, 2017 |
| Grant date | Dec 25, 2018 |
| Priority date | — |
| Expiry date | May 12, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/1819
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Concepts and schemes pertaining to quasi-cyclic-low-density parity-check (QC-LDPC) coding are described. A processor of an apparatus may generate a QC-LDPC code having a plurality of codebooks embedded therein. The processor may select a codebook from the plurality of codebooks. The processor may also encode data using the selected codebook. Alternatively or additionally, the processor may generate the QC-LDPC code including at least one quasi-row orthogonal layer. Alternatively or additionally, the processor may generate the QC-LDPC code including a base matrix a portion of which forming a kernel matrix that corresponds to a code rate of at least a threshold value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.