Method and apparatus for differential power analysis (DPA) resilience security in cryptography processors
US10164768B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 23, 2018 |
| Grant date | Dec 25, 2018 |
| Priority date | — |
| Expiry date | Feb 23, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/125
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In certain aspects, a circuit includes a dynamic differential logic gate having first and second outputs, and a first static differential logic gate having first and second outputs, and first and second inputs coupled to the first and second outputs, respectively, of the dynamic differential logic gate. The dynamic differential logic gate is configured to receive a clock signal and to preset both the first and second outputs of the dynamic differential logic gate to a first preset value during a first phase of the clock signal. The first static differential logic gate is configured to preset both the first and second outputs of the first static differential logic gate to a second preset value when the first preset value is input to both the first and second inputs of the first static differential logic gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.