Incremental update of the data plane of a hardware forwarding element
US10164829B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 21, 2017 |
| Grant date | Dec 25, 2018 |
| Priority date | — |
| Expiry date | Aug 21, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L45/745
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method of incremental updating of a network forwarding element that includes (i) a set of data plane circuits with a set of ingress buffers and a group of configurable packet processing stages and (ii) a set of control plane circuits comprising a set of direct memory access (DMA) buffers. Configuration data for reconfiguring the data plane packet processing stages is loaded into the DMA buffers while the packet processing stages are processing the packets. The ingress buffers are configured to (i) pause sending the packets to the processing stages and (ii) continue storing the incoming packets while sending the data plane packets to the processing stages is paused. The configuration data is loaded from the DMA buffers into the packet processing stages. The ingress buffers are configured to resume sending the data packet plane packets to the packet processing stages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.