Scan chain latency reduction

US10168386B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• George Antony · Thrissur, IN
• Mary P. Kusko · Poughkeepsie, US
• Sridhar H. Rangarajan · Savanuru, IN
• Shrinivas Shenoy · Bengaluru, IN

Key dates

• Filing date: Jan 13, 2017
• Grant date: Jan 1, 2019
• Expiry date: Feb 19, 2037

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/318563
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A method, executed by a computer, includes receiving a scan chain design comprising a plurality of parallel scan chains, each parallel scan chain comprising one or more serially connected single-bit registers, each parallel scan chain having a scan chain length. The plurality of parallel scan chains are interspersed with a plurality of stumpmuxes that enable access to the plurality of parallel scan chains and segment each parallel scan chain into a plurality of scan chain segments. The method further includes conducting a determining operation comprising determining a parallel scan chain having a longest scan chain length, and conducting a swapping operation comprising swapping scan chain segments attached to a selected stumpmux to reduce the longest scan chain length and produce an updated scan chain design. A computer system and computer product corresponding to the above method are also disclosed herein.