Technique for sub-microsecond latency measurement across a bus
US10168730B2 · kind B2 · utility
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5References
21Claims
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Key dates
| Filing date | Mar 10, 2014 |
| Grant date | Jan 1, 2019 |
| Priority date | — |
| Expiry date | Jul 29, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and systems for determining latency across a bus, such as a PCIe bus, coupling a field programmable gate array (FPGA) and a processor having different time incrementation rates. Both the FPGA and the processor count clock ticks independently, and using a calibration offset and the two incrementation rates, the processor converts the FPGA clock ticks into processor clock ticks in order to determine latency across the bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.