Circuit for addition of multiple binary numbers
US10168991B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2016 |
| Grant date | Jan 1, 2019 |
| Priority date | — |
| Expiry date | Feb 8, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/509
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit is provided for addition of multiple binary numbers. The circuit includes a 4-to-2-compressor configured for calculating a compressed representation from four binary numbers received via operand inputs of the 4-to-2-compressor. The 4-to-2-compressor includes a first sub-circuit and a second sub-circuit. Each of the first sub-circuit and the second sub-circuit is configured for transmitting a bitwise inverted representation, of a compressed representation, from three binary numbers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.