Patent · US Active

Translation lookaside buffer purging with concurrent cache updates

US10169233B2 · kind B2 · utility

0Cited by

14References

20Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Simon H. Friedmann · Eppelheim, DE
Markus Kaltenbach · Holzgerlingen, DE
Dietmar Schmunkamp · Schenefeld, DE
Johannes C. Reichart · Highland, US

Key dates

Filing date	Jun 5, 2017
Grant date	Jan 1, 2019
Priority date	—
Expiry date	Jun 5, 2037

Classification

Technology area (CPC G)Physics
CPC primaryG06F2212/68
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method and computer processor performs a translation lookaside buffer (TLB) purge with concurrent cache updates. Each cache line contains a virtual address field and a data field. A TLB purge process performs operations for invalidating data in the primary cache memory which do not conform to the current state of the translation lookaside buffer. Whenever the TLB purge process and a cache update process perform a write operation to the primary cache memory concurrently, the write operation by the TLB purge process has no effect on the content of the primary cache memory and the cache update process overwrites a data field in a cache line of the primary cache memory but does not overwrite a virtual address field of said cache line. The translation lookaside buffer purge process is subsequently restored to an earlier state and restarted from the earlier state.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.