Variation-aware circuit simulation
US10169507B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2017 |
| Grant date | Jan 1, 2019 |
| Priority date | — |
| Expiry date | Mar 24, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02E60/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integration circuit (IC) simulation method includes: (a) providing a design netlist of a system-level circuit, wherein the system-level circuit comprises a first sub-circuit; (b) providing a first behavior model that is determined based on an operation of the first sub-circuit, wherein the first behavior model is a function of one or more respective behavior-level parameters; (c) incorporating a first variation into each of the one or more behavior-level parameters of the first behavioral model; and (d) simulating the system-level circuit based on the one or more behavior-level parameters of the first behavior model that incorporates the first variation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.