Gate line layout configuration
US10170072B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 21, 2015 |
| Grant date | Jan 1, 2019 |
| Priority date | — |
| Expiry date | Jan 22, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2330/021
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A display device may include pixels and source lines that provide data line signals to the pixels. The display device may also include gate lines that provide gate signals to switches associated with the pixels. The display device may also include vertical gate lines disposed generally parallel to the source lines and coupled to the gate lines at cross point nodes. The display device may also include compensation lines, such that each compensation line is proximate to a respective vertical gate line. The compensation lines may transmit compensation signals having an opposite polarity as compared to respective gate signals to reduce or eliminate a kickback voltage on at least one of the plurality of pixels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.