Threshold voltage shifting at a lower bit error rate by intelligently performing dummy configuration reads
US10170195B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 6, 2017 |
| Grant date | Jan 1, 2019 |
| Priority date | — |
| Expiry date | Dec 6, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A controller adapts read voltage thresholds of a non-volatile memory. In one embodiment, in response to selection of a block for adaptation of at least one read voltage threshold applicable to a physical page of the block, the controller issues a dummy read operation to the block to ensure the physical page is in a lower bit error rate (BER) state. The controller waits for a calibration read wait period following the dummy configuration read operation and, during the calibration read wait period, monitors for an interfering access to the non-volatile memory that would temporarily place the physical page in a higher BER state. In response to not detecting the interfering access during the calibration read wait period, the controller performs a calibration read operation for the physical page and adapts at least one read voltage threshold for the physical page based on results of the calibration read operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.