Transistor array panel and manufacturing method thereof
US10170502B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 15, 2016 |
| Grant date | Jan 1, 2019 |
| Priority date | — |
| Expiry date | Dec 15, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K59/131
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A transistor array panel is manufactured by a method that reduces or obviates the need for highly selective etching agents or complex processes requiring multiple photomasks to create contact holes. The panel includes: a substrate; a buffer layer positioned on the substrate; a semiconductor layer positioned on the buffer layer; an intermediate insulating layer positioned on the semiconductor layer; and an upper conductive layer positioned on the intermediate insulating layer, wherein the semiconductor layer includes a first contact hole, the intermediate insulating layer includes a second contact hole positioned in an overlapping relationship with the first contact hole, and the upper conductive layer is in contact with a side surface of the semiconductor layer in the first contact hole.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.