Transistor panel having a good insulation property and a manufacturing method thereof
US10170626B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 23, 2017 |
| Grant date | Jan 1, 2019 |
| Priority date | — |
| Expiry date | Mar 8, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K59/1213
Abstract
A transistor panel includes a channel region including an oxide of a first metal, a source region and a drain region, each including the first metal, wherein the channel region is disposed between the source and drain regions, and wherein the channel region is connected to the source and drain regions, an insulation layer disposed on the channel region, an upper electrode disposed on the insulation layer, an interlayer insulation layer disposed on the upper electrode, the source region and the drain region, and a barrier layer including a first portion disposed between the interlayer insulation layer and each of the source and drain regions, wherein the first portion of the barrier layer contacts each of the source and drain regions. The upper electrode and the barrier layer each comprise a second metal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.