Power factor correction circuit and multiplier
US10171035B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 25, 2016 |
| Grant date | Jan 1, 2019 |
| Priority date | — |
| Expiry date | Jan 25, 2036 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02B70/10
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention disclosure provides a multiplier and a power factor correction circuit which the multiplier is applied. The multiplier comprises a Gilbert multiplier circuit comprising a first differential input stage, a second differential input stage and an output stage; a first differential voltage conversion circuit; a second differential voltage conversion circuit; and a bias current generating circuit; Wherein said output stage comprises: a current mirror unit comprising two current input terminals and a current output terminal; and a feedback control unit configured to ensure that the current output terminal does not output current when the voltage difference received by the multiplier is zero. The present invention is advantageous in improving the linearity of the multiplier and the accuracy of the output current of the multiplier output current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.