Time clock signal processing system and method thereof
US10171092B2 · kind B2 · utility
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8Claims
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Key dates
| Filing date | Apr 7, 2017 |
| Grant date | Jan 1, 2019 |
| Priority date | — |
| Expiry date | Apr 7, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/093
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A time clock signal processing system and method thereof, applicable to an environment of USB synchronous mode audio clock reconstruction, is disclosed. The clock signal processing method employed by the clock signal processing system first uses a first-stage phase-locked loops (PLL) to raise the frequency of the inputted USB start-of-frame (SOF) field, provides clock synchronization and outputs the second-stage PLL; then, the second-stage PLL reduces the timing jitter of the output of the first-stage PLL to below 20 ps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.